Design Verification Engineer Active
- Develop verification environment of block, system and chip
- Develop entire verification flow including test plan,
implementation (tests and simulation) and coverage
- Implement design using Verilog HDL/VHDL.
- Develop methodologies, scripts and infrastructure
- B.Sc. in Computer Engineering.
- Knowledge of Object-Oriented Programming (OOP) is a must.
- Knowledge of data structure and algorithms is a must.
- Knowledge of Digital/Analog circuits is must.
- Knowledge of Hardware Description Language (Verilog HDL or
VHDL) is a must.
- Knowledge of Unix/Linux – advantage.
- Knowledge of integration, debugging, functional verification
and test plan development – advantage.
- Knowledge of system level, chip level, and Block level
verification and test bench development – advantage.
- Strong communication skills.
- Independent learner\worker and problem-solver.
- Out of the box thinking.