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Design Verification - Train to Hire Active

ASAL has an exciting opportunity for fresh graduates in the field of Design Verification. You will be attending practical training and be part of a team of engineers who’ll help you in getting insights on developing, establishing and maintaining quality engineering methodologies, systems, and practices 

 What You'll Need:

  • B.Sc. in Computer/Electrical/Electronic Engineering.
  • Knowledge in Object-Oriented Programming (OOP) is necessary.
  • Knowledge of data structure and algorithms is necessary.
  • Knowledge of Digital/Analog circuits is necessary.
  • Knowledge in Verilog HDL or VHDL language is necessary.
  • Knowledge of Unix/Linux – advantage.
  • Knowledge in integration, debugging, functional verification and test plan development – advantage.
  • Knowledge of system level, chip level, and Block level verification and test bench development – advantage.

 What You'll Do:

  • Develop a verification environment of block, system and chip levels.
  • Develop an entire verification flow including test plan, implementation (tests and simulation) and coverage collection.   
  • Implement design using Verilog HDL and VHDL.
  • Develop methodologies, scripts and infrastructure improvements.