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Senior Design Verification Engineer Active


Job Descriptions:

-        Develop verification environment of block, system and chip levels.

-        Develop entire verification flow including test plan, implementation (tests and simulation) and coverage collection.

-        Implement design using Verilog HDL and VHDL.

-        Develop methodologies, scripts and infrastructure improvements.


Job Qualifications:

-       Bachelor’s degree in Computer/Electrical/Electronic Engineering, or a related field, or equivalent alternative education, skills, and/or practical experience.

-        4+ years’ experience developing verification environment (tests and simulation).

-        Experience in System Verilog one of Verification languages.

-        Experience in Verilog HDL or VHDL language.

-        Experience in Digital/Analog circuits.

-        Experience in scripting languages.

-        Experience in integration, debugging, functional verification and test plan development.

-        Experience in system level, chip level, and Block level verification and test bench development.

-        With technical passion and terrific problem-solving skills to drive for result and impact.

-        The ability to fully understand problem spaces and independently drive areas forward.

-        Excellent written and verbal communication skills in English.

-        Effective communication skills and ability to work in a collaborative environment.

-        A commitment to teamwork and self-motivation.