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Design Verification Engineers Active

Description:

  • Develop verification environment of block, system and chip levels.
  • Develop entire verification flow including test plan, implementation (tests and simulation) and coverage collection.   
  • Implement design using Verilog HDL and VHDL.
  • Develop methodologies, scripts and infrastructure improvements.

 

 Requirements

  • B.Sc. in Computer/Electrical/Electronic Engineering.
  • Knowledge in Object-Oriented Programming (OOP) is a must.
  • Knowledge of data structure and algorithms is a must.
  • Knowledge of Digital/Analog circuits is must.
  • Knowledge in Verilog HDL or VHDL language is a must.
  • Knowledge of Unix/Linux – advantage.
  • Knowledge in integration, debugging, functional verification and test plan development – advantage.
  • Knowledge of system level, chip level, and Block level verification and test bench development – advantage.